1. Technical Field
The present invention described herein relates to a semiconductor memory apparatus and, more particularly, to an address control circuit of a semiconductor memory apparatus.
2. Related Art
Semiconductor memory apparatuses, particularly, volatile semiconductor memory apparatuses have been known to vary an original data level as data recorded in a memory cell elapses. That is, data can be compromised and subsequently lost.
Therefore, in the semiconductor memory apparatuses, it is essential that a refresh operation for maintaining a data level recorded in a memory cell must be performed.
The refresh operation of the semiconductor memory apparatus can be divided into an auto refresh operation that is performed depending on an external command and into a self refresh operation that is internally performed at a predetermined cycle.
Since the self refresh operation is internally performed in the semiconductor memory apparatus not by the external command, a circuit component for designating a refresh address for a cyclic refresh operation is required.
Therefore, the semiconductor memory apparatus is provided with an address control circuit as a circuit for generating the refresh address and selectively providing a normal address inputted from the outside for an active operation, i.e., a read or write operation, and that the refresh address to a memory area is referred to as a bank.
As shown in FIG. 1, the address control circuit 10 can include a counter block 11 and a latch block 12.
The counter block 11 can generate refresh addresses ‘RRA<0:12>’ by counting a refresh signal ‘REF’.
The latch block 12 can generate bank addresses ‘BX<0:12>’ for latching and providing normal addresses ‘AT<0:12>’ or the refresh addresses ‘RRA<0:12>’ to the bank depending on an active pulse signal ‘ATCP’ and the refresh signal ‘REF’.
Further, although not shown in FIG. 1, an address buffer for receiving an external address and a decoder for generating the normal addresses ‘AT<0:12>’ by decoding the output of the address buffer are provided. The address buffer, particularly, an address buffer that receives a row address related to the refresh operation stops to operate to reduce current during the refresh operation.
Since the refresh addresses ‘RRA<0:12>’ are sequentially increased by the counter block 11, values of the refresh addresses ‘RRA<0:12>’ cannot be known during the refresh operation and the refresh addresses cannot be changed outside of the semiconductor memory apparatus.
As such, in the semiconductor memory apparatus, the values of the refresh addresses ‘RRA<0:12>’ cannot be known during the refresh operation and the refresh addresses cannot be changed. Therefore, when a failure occurs during the refresh operation, the relevant failure details cannot be grasped.